JM20337 DATASHEET PDF

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Version 1. Mar All rights reserved. Page 1. Copying prohibited. Revision History. Revision Description. Initialization of this document. Correct typo. Add package outline. Update electrical characteristics. In no event will JMicron.

All Rights Reserved. Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice.

The products described in this document are NO T intended for use implantation or other life supports application where malfunction may result in injury or death to persons. Nothing in this document shall operate as an express or implied license or environments, and is presented as an illustration. The results obta ined in other operating environments may vary. Page 2. Table of Contents. General Description. Main Applications. Block Diagram. Package and Pin Assignments.

Pin Descriptions. Electrical Characteristics. Page 3. This chip is designed by 0. Compliance with USB 2.

Page 4. Figure 2 Block Diagram. Page 5. Figure 3 Package Pin Assignment. Page 6. Pin Name. Page 8. Pin Type. Signal Name. Pin No. External Reference Resistance. SATA Analog 1. This power could be sourced from internal 1. Analog Probe Pin. This pin is an analog probe pin, and should be reserved as No Connection NC in normal operation.

SATA Analog 3. USB Interface. USB Analog 3. USB Analog Ground. Page 9. It is connected to a 12MHz crystal or crystal oscillator. Crystal Output. It is connected to a crystal. While crystal oscillator is applied, this pin should be reserved as No Connection NC. Voltage Regulator. Voltage Regulator 1. Voltage Regulator 3.

Voltage Regulator Ground. Parallel ATA Interface. Digital 3. Digital 1. Digital Ground. System Global Reset Input. Active-low to reset the entire chip. An external 10msec RC should be connected to this pin.

While chip in reset state, all the PATA bus is tri-state. Test Mode Enable. This pin is reserved for IC mass production testing. General Purpose IO Interface. Page The functionality of power on initial state determines the PATA interface pin order configuration. The functionality of power on initial state is as below. Normal Order. Reverse Order. Analog power supply. Storage temperature. Recommended Power Supply Operation Conditions.

Operation digital power supply. Operation analog power supply. Ambient operation temperature. Junction temperature. Recommended External Clock Source Conditions. External reference clock. Clock Duty Cycle. Power Supply DC Characteristics. Internal voltage regulator. Rising slew-rate. Falling slew-rate.

Device Capacitance. C device. DC sink current. Internal pull-up current. Input low-voltage. Input high-voltage. Output low-voltage. Output high-voltage. Byte 0. Byte 1. By te 2.

By te 3.

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