While these implementations successfully achieve the performance goal they fall short in addressing the requirements of smaller area, lower power and reduced routing congestion. By eliminating redundant logic and wires designers are able to realize lower area, power and reduced routing congestion. Automated configuration and assembly with Synopsys' coreAssembler tool enables the IP to be rapidly deployed into the design environment. Up till now the standard AMBA 3 AXI interconnect fabric implementation only targets the high performance SoC requirement by offering a multiple address, multiple data architecture which supports parallel traffic from independent masters and slaves. On a per port basis you have independent write and read, data and response channels resulting in this type of architecture being able to support even the most demanding system bus bandwidths requirements. While many component connections within a high performance SoC will require such a high bandwidth, there are also masters and slave connections which do not.

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UFS Host 3. USB 2. Accelerating 5G virtual RAN deployment. RoT: The Foundation of Security. Managing connected devices at scale: Connect millions of shipments on one platform. Arm Mali Best Practices 2. The need for higher performance applications is driving the requirement for a new age of on-chip communication infrastructure. Increasing the clock frequency no longer addresses this higher performance requirement, as the bottleneck is inherent in the existing bus infrastructure.

It describes the AMBA 3 AXI protocol feature set that makes it suitable for the new high-performance, low-latency and low-power designs. As design complexity continues to increase, time-to-market pressures force shorter and shorter design cycles. High-performance designs are technically complex and require vast amounts of verification to ensure correct operation.

Interconnect topologies, with multiple address, data, handshaking buses and transaction cycles that complete out of order over many cycles, enable high performance and low latency, but can no longer be verified with the standard directed testing methodologies. These features on their own not only take the verification task to the next level of complexity, but also introduce corner cases that must be captured and tested.

Unfortunately these corner cases are typically very hard to identify and, if missed, could mean failure of the resulting design. One way to reduce the risk and pressures of a new design is through the use of standards and reuse.

Today, designers can also choose from a range of open specifications of on-chip interface protocols. Choosing this option facilitates use of proven, pre-designed, pre-verified IP and verification components.

With more proven IP in the design and by the deployment of Verification IP VIP , designers can focus on differentiating their designs rather than verification of the standard based protocol. Use of existing standard protocol IP and VIP shortens subsystem creation time, as less effort and time is required to build and verify the SoC infrastructure. The use of these standards-based protocols also aids interoperability, as all components will have been designed to the same specification.

This dramatically reduces the overall risk associated with the design. These are the latest generation protocols, which are interoperable with existing bus technology defined in the AMBA 2 Specification. This open access, coupled with the advanced features that AMBA 3 AXI provides, makes it a good candidate to be the de-facto standard for the next generation of on-chip bus interconnects.

This is even worse when designing to a protocol that you have not implemented before. In addition to design application testing, significant effort is needed to learn the new protocol to make use of the features the protocol brings to the design.

The huge set of complicated verification tasks is driving designers to become smarter about verification, which includes choosing the right tools and techniques. Directed testing no longer generates enough coverage in the time allotted, so other approaches are required.

The AMBA 3 AXI protocol defines a unidirectional channel architecture, which enables the efficient use of register slices to pipeline the connection for higher speeds, or to enable the use of multiple clock domains for low power. A clear advantage of this interoperability is that designers have access to a wide array of silicon-proven IP and VIP for AMBA protocols, increasing options for reuse and again increasing the time designers spend on design differentiation rather than general subsystem creation and validation.

The AMBA 3 AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for a high-speed, submicron interconnect. No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.

Design And Reuse. Codasip Blog - Roddy Urquhart. Managing connected devices at scale: Connect millions of shipments on one platform arm Blogs - Jennifer Sillars, Arm. The Ever Reducing Development Cycle As design complexity continues to increase, time-to-market pressures force shorter and shorter design cycles. Standards and Reuse One way to reduce the risk and pressures of a new design is through the use of standards and reuse. The information source uses the VALID signal to show when valid data or control information is available on the channel.

Both the read data channel and the write data channel also include a LAST signal to indicate when the transfer of the final data item within a transaction takes place. Read and write transactions each have their own address channel. The appropriate address channel carries all of the required address and control information for a transaction. The Read data channel conveys both the read data and any read response information from the slave back to the master.

The Read data channel includes the data bus, which can be 8, 16, 32, 64, , , , or bits wide and a read response indicating the completion status of the read transaction. The Write data channel conveys the write data from the master to the slave. The Write data channel includes the data bus, which can be 8, 16, 32, 64, , , , or bits wide, and one byte lane strobe for every eight data bits, which indicates which bytes of the data bus are valid.

Such systems can achieve a good balance between system performance and interconnect complexity by using a shared address bus with multiple data buses to enable parallel data transfers. When one master sends an address to one slave, no other master can use the address bus. This is similar to the structure of the AMBA 2 specification. With SAMD, one master and slave can be active per address channel. For example, if master1 sends write data to slave1, master2 can send write data to slave2 at the same time and does not have to wait for the bus being freed.

The number of active pairs is design dependent. Obviously the parallel nature of this operation significantly improves the performance of the subsystem. With MAMD, multiple pairs can be active on the address channels. This provides the maximum of interconnect flexibility and yields the highest performance subsystem interconnect architecture. This topology is also the most complex scenario to verify as multiple masters and slaves can be active at any time.

Verifying the interaction between all ports will be critical to the successful operation of the resulting system. Deployment of a Layered Constrained Random Verification Methodology Deployment of a layered verification methodology, combined with the use of constrained random verification techniques, are required to meet the challenge of verifying a subsystem which uses the AMBA 3 AXI protocol. As discussed earlier, a directed testing methodology cannot create enough system stimuli to reach the required coverage goals in the shortened design cycle.

The Synopsys Reference Verification Methodology RVM is one example of a reusable layered verification methodology that employs constrained random techniques to achieve full coverage in the shortest possible time and effort. Reuse is another key consideration with verification as well as with IP. The verification methodology must support reuse such that tests at one hierarchical level can me reused at the next level up, as well as with the next project.

The structure of RVM enables this. With a layered verification approach, lower layers like protocol verification are reused at higher levels.

Tests written for the lowest levels, protocol validation are reused at the higher levels where the verification focus shifts to generating and verifying transaction sequences that not only stress the bus interface logic but can also target the application-specific logic. Leveraging Verification IP and Assertion IP A new interface like the AMBA 3 AXI protocol requires additional verification to ensure that the protocol has been implemented correctly and to ensure that none of the included components violate the protocol standard.

This requires the generation of verified stimuli, responses and some sort of monitor to check that all transactions adhere to the protocol standard. One solution would be to create hand-crafted protocol transactors to generate the desired stimuli.

Example costs that have to be considered include the time it takes to create this transactor, ensuring adherence to the protocol, supporting it throughout the design cycle, and designing it for reuse in subsequent projectsl. Of course, the actual transactor will require its own verification environment to ensure some level of accuracy. Finally, this hand-crafted verification block will need to support a layered methodology with the generation of constrained random transactions if it is really going to help with the verification task.

A better approach to take is to use VIP from a reliable vendor, like Synopsys, who has done the hard work to verify the accuracy of the generated protocol and implemented the required interfaces to enable the use of the layered methodology with constrained random transaction generation.

The Synopsys monitor for the AMBA 3 AXI protocol is used to verify the bus protocol, generate bus coverage and cross port coverage information and has the required hooks to support a self-checking scoreboard-based testbench.

The VIP provides the advanced simulation features like cross-port coverage and scoreboard notification. The assertion IP can be used as the golden reference and enables the use of formal tools and techniques.

The layered approach is applied to individual block-level verification as well as at the subsystem and full system level. Each layer of tests builds on top of each other, so moving from layer to layer requires minimal effort. Each layer of tests is portable so it can be reused at a subsequent layer or within a new verification project. There are fundamentally three layers: The layer 1 tests target interface protocol verification while layers 2 and 3 target application-specific logic verification using realistic data traffic generation which stresses the subsystem more completely.

Fig 5: Verification Layers Layer 1 The goal of layer 1 is to test the physical bus interface and ensure that it does not violate bus protocols. Once all basic transactions have been covered, layer 2 tests can begin. The Synopsys master and slave VIP can be used to generate the bus testing cycles while the monitor can be used to check the interface protocol while automatically collecting transaction coverage data.

Layer 2 The goal of layer 2 is to generate transaction sequence tests that not only stress the bus interface logic, but also target the application-specific logic. Layer 2 tests are structured to generate realistic design traffic. To fully achieve the layer 2 goals, constrained random techniques must be applied to the verification environment. With a couple of simple bus functional commands, you can generate correct bus cycles.

The Synopsys RVM provides the infrastructure to generate these constrained random transactions with ease and enable reuse at each subsequent layer and reuse across projects.

High bus cycle and functional coverage are achieved very quickly and more corner cases will be found. The coverage statistics will be far more complete than what could be achieved using directed tests only. This constrained random environment is able to generate huge amounts of stimuli from a minimum of testbench code.

As it is constrained to the design requirements, simulation cycles are not wasted by inadvertently activating unnecessary sections of the subsystem. The constrained random traffic will stress the design block under verification far more than directed tests can. A fully constrained random environment is defined as a set of transactions with a layer of sequences above that, then a layer of choices sitting above with the final layer being the transaction constraints.

The payload is fed into the system, which creates an autonomous stimuli generator. Individual transactions are joined together to create a sequence.

Sets of sequences are joined together to create a choice. Sets of choices will produce a wide variety of transaction cycles and responses. Full sign-off scenarios are run, which include system and application boot sequences. The software-to-software interfaces can be checked at this level. Now, a full context validation can be achieved. The layer 3 tests target the higher-level functions of either the individual block or system.


Advanced eXtensible Interface

AMBA AXI specifies many optional signals , which can be optionally included depending on the specific requirements of the design, [2] making AXI a versatile bus for numerous applications. While the communication over an AXI bus is between a single master and a single slave, the specification includes detailed description and signals to include N:M interconnects, able to extend the bus to topologies with more masters and slaves. Thread IDs allow a single master port to support multiple threads, where each thread has in-order access to the AXI address space, however each thread ID initiated from a single master port may complete out of order with respect to each other. For instance in the case where one thread ID is blocked by a slow peripheral, another thread ID may continue Independent of the order of the first thread ID. Another example, one thread on a cpu may be assigned a thread ID for a particular master port memory access such as read Addr1, write addr1, read addr1, and this sequence will complete in order because each transaction has the same master port thread ID.


AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite

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AMBA 3 AXI with Hybrid Architecture


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